Coherent optical communication links at rates of 100 Gbps/λ and higher have been commercially deployed in recent years. These systems heavily rely on power-hungry (e.g., >10 W) digital signal processing (DSP) devices even for cutting-edge CMOS process technologies (e.g., 16 nm linewidths in commercial products). The ability to support unamplified links of up to 80 km at such high rates justifies the cost of powerful DSPs in light of a reduction of other capital expenses and operating costs. On the other hand, the ever-increasing demand for high bandwidth communications within data centers is pushing direct-detection, intensity modulation four-level pulse amplitude modulation (PAM4) schemes to their limits.
For example, IEEE P802.3cd is expected to standardize as one of its PHY options, 100GBASE-DR, 100 Gb/s serial transmission over one wavelength using PAM4 over of single-mode fiber >500 m. Results from contributors to the IEEE P802.3cd task group, shown in FIG. 1 (IEEE SMF Task Group Contribution by Marco Mazzini (Cisco), August 2014), indicate that 56 Gbaud/112 Gbps PAM4 requires a feed-forward equalizer to open the eye. Although some approaches have demonstrated feasibility, numerous contributions indicate that meeting link budget margins for this type of PHY option remains challenging.
Accordingly, what is needed are systems and methods that obtain the benefits of coherent modulation schemes, while avoiding the major cost and power consumption of DSP-heavy approaches that oftentimes require extremely high sample rate ADCs and equalizers.